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1 publication order number : lb11696v/d www.onsemi.com ? semiconductor components industries, llc, 2015 march 2015 - rev. 1 ordering information see detailed ordering and shipping info rmation on page 17 of this data sheet. lb11696v overview the lb11696v is a direct pwm drive predriver ic designed for three- phase power brushless motors. a motor driver circuit with the desired output power (voltage and current) can be implemented by adding discrete transistors in the output circuits. furthermore, the lb11696v provides a full complement of protection circuits allowing it to easily implement high-reliability drive circuits. this device is optimal for driving all types of large-scale motors such as those used in air conditioners and on-demand water heaters. features ? three-phase bipolar drive ? direct pwm drive (controlled either by cont rol voltage or pwm variable duty pulse input) ? built-in forward/reverse switching circuit ? start/stop mode switching circuit (stop mode power saving function) ? built-in input amplifier ? 5 v regulator output (vreg pin) ? current limiter circuit (supports 0.25 v (typical) reference voltage sensing based high-precision detection) ? undervoltage protection circuit (the operating voltage can be set with a zener diode) ? automatic recovery type constraint protection circuit with protection operating state discrimination output (rd pin) ? four types of hall signal pulse outputs ? supports thermistor based thermal protection of the output transistors specifications absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit supply voltage 1 v cc max v cc pin 18 v output current i o max ul, vl, wl, uh, vh, and wh pins 30 ma lvs pin applied voltage lvs max lvs pin 18 v allowable power dissipation 1 pd max 1 independent ic 0.45 w allowable power dissipation 2 pd max 2 when mounted on a 114.3 ? 76.1 ? 1.6 mm glass epoxy board 1.05 w operating temperature topr ?20 to +100 ? c storage temperature tstg ?55 to +150 ? c monolithic digital ic direct pwm drive brushless motor predriver ic stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. ssop30 (275mil)
lb11696v www.onsemi.com 2 allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit supply voltage range 1-1 v cc 1-1 v cc pin 8 to 17 v supply voltage range 1-2 v cc 1-2 v cc pin, when v cc is shorted to vreg. 4.5 to 5.5 v output current i o ul, vl, wl, uh, vh, and wh pins 25 ma 5 v constant voltage output current ireg hp pin applied voltage vhp 0 to 17 v hp pin output current ihp 0 to 15 ma rd pin applied voltage vrd 0 to 17 v rd pin output current ird 0 to 15 ma electrical characteristics at ta = 25 c, v cc = 12 v parameter symbol ratings unit min typ max current drain 1 i cc 1 12 16 ma current drain 2 i cc 2 2.5 4 ma [5 v constant voltage output (vreg pin)] output voltage vreg 4.7 5.0 5.3 v line regulation vreg1 v 40 100 mv load regulation vreg2 i 10 30 mv temperature coefficient 0 [output block] output voltage 1-1 v out output voltage 1-2 v out output voltage 2 v out output leakage current i o leak [hall amplifier block] input bias current ihb (ha) common-mode input voltage range 2 vicm2 hall input sensitivity hysteresis vin (ha) input voltage low high vslh (ha) input voltage high low vshl (ha) [ctl amplifier] input offset voltage v io (ctl) input bias current i b (ctl) common-mode input voltage range vicm high-level output voltage v oh low-level output voltage v ol open-loop gain [pwm oscillator (pwm pin)] high-level output voltage v oh (pwm) low-level output voltage v ol (pwm) external capacitor charge current ichg vpwm = 2.1 v oscillator frequency f (pwm) c = 2000 pf amplitude v (pwm) [toc pin] input voltage 1 vtoc1 output duty: 100% 2.68 3.0 3.34 v input voltage 2 vtoc2 output duty: 0% 1.2 1.35 1.5 v input voltage 1 low vtoc1l design target value, when vreg = 4.7 v, 100% 2.68 2.82 2.96 v input voltage 2 low vtoc2l design target value, when vreg = 4.7 v, 0% 1.23 1.29 1.34 v input voltage 1 high vtoc1h design target value, when vreg = 5.3 v, 100% 3.02 3.18 3.34 v input voltage 2 high vtoc2h design target value, when vreg = 5.3 v, 0% 1.37 1.44 1.50 v [hp pin] output saturation voltage vhpl i o = 10 ma 0.2 0.5 v output leakage current ihpleak v o = 18 v 10 a continued on next page. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lb11696v www.onsemi.com 3 parameter symbol conditions ratings unit min typ max [csd oscillator (csd pin)] high-level output voltage v oh (csd) low-level output voltage v ol (csd) external capacitor charge current ichg1 vcsd = 2 v external capacitor discharge current ichg2 vcsd = 2 v charge/discharge current ratio rcsd (charge current)/(discharge current) times [rd pin] low-level output voltage vrdl i o = 10 ma output leakage current i l (rd) v o = 18 v [current limiter circuit (rf pin)] limiter voltage vrf rf-rfgnd [undervoltage protection circuit (lvs pin)] operating voltage vsdl release voltage vsdh hysteresis vsd [pwmin pin] input frequency f (pi) khz high-level input voltage v ih (pi) low-level input voltage v il (pi) input open voltage v io (pi) hysteresis v is (pi) high-level input current i ih (pi) vpwmin = vreg low-level input current i il (pi) vpwmin = 0 v a [s/s pin] high-level input voltage v ih (ss) low-level input voltage v il (ss) hysteresis v is (ss) high-level input current i ih (ss) vs/s = vreg low-level input current i il (ss) vs/s = 0 v a [f/r pin] high-level input voltage v ih (fr) low-level input voltage v il (fr) input open voltage v io (fr) hysteresis v is (fr) high-level input current i ih (fr) vf/r = vreg low-level input current i il (fr) vf/r = 0 v a [n1 pin] high-level input voltage v ih (n1) low-level input voltage v il (n1) input open voltage v io (n1) high-level input current i ih (n1) vn1 = vreg low-level input current i il (n1) vn1 = 0 v a [n2 pin] high-level input voltage v ih (n2) low-level input voltage v il (n2) input open voltage v io (n2) high-level input current i ih (n2) vn2 = vreg low-level input current i il (n2) vn2 = 0 v a continued from preceding page. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lb11696v www.onsemi.com 4 input state n1 pin n2 pin hp output l l single hall sensor period divided by 2 l high or open single hall sensor period high or open l three hall sensor synthesized period divided by 2 high or open high or open three hall sensor synthesized period n1 and n2 pins since the s/s pin does not have an internal pull-up resistor, an external pull-up resistor or equivalent is required to s et the ic to the stop state. if either the s/s or pwmin pins are not used, the unused pin input must be set to the low-lev el voltage. the hp output can be selected (by the n1 and n2 settings) to be one of the following four functions: the in1 hall inp ut converted to a pulse output (one-hall output), the one-hall output divided by two, the three-phase output synthesiz ed from the hall inputs (three-hall synthesized output) or the three-hall synthesized output divided by two. input state state h stop l start s/s pin input state state high or open output off l output on pwmin pin f/r = l f/r = h output 1hlhlhlv hu l 2hlllhhw hu l 3hhlllhw hv l 4lhlhlhu hv l 5lhhhllu hw l 6llhhhlv hw l 0.8 1 1.05 0.4 0.45 0.6 0.2 0 1.2 0 20 40 60 80 120 100 0.42 0.18 allowable power dissipation, pdmax w 114.3mm 76.1mm 1.6mm glass epoxy board independent
lb11696v www.onsemi.com 5 package dimensions unit : mm ssop30 (275mil) case 565at issue a soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. (unit: mm) 7.00 0.32 1.00 0.65 xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxxxx ymddd to
page. 6 lb11696v pin functions pin no. symbol pin description equivalent circuit 1 gnd ground 2 rf gnd output current detection reference connect the ground terminal of the external resistor rf to this pin. vreg 2 continued on next page. 3 rf output current detection connect a resistor with a small value between this pin and rfgnd. this sets the maximum output current i out to be 0.25/rf. vreg 3 4 6 8 5 7 9 wh vh uh wl vl ul outputs (external transistor drive outputs) the duty control applies to the uh, vh, and wh pins. 4 6 8 5 7 9 v cc 50 k pin assignment v cc vreg n2 n1 hp f/r rfgnd rf wh wl lb11696v vl top view pwmin s/s csd uh ul in1C in1+ vh lvs 9 8 7 6 5 4 3 2 1 10 11 12 13 14 15 27 26 28 24 23 25 21 29 22 30 19 18 20 16 17 in2C in2+ in3C in3+ ei+ rd pwm toc eiC gnd
page. 7 lb11696v pin no. pin name pin description equivalent circuit 18 toc control amplifier output when the toc pin voltage rises, the ic changes the uh, vh, and wh output signal pwm duty to increase the torque output. vreg 18 300 40 k 19 pwm shared function pin: pwm oscillator frequency setting and initial reset pulse generation insert a capacitor between this pin and ground. a capacitor of 2000 pf sets a frequency of about 22 khz. 200 19 2 k vreg 20 rd motor constraint detection output this pin output is on when the motor is turning and off when the constraint protection circuit operates. vreg 20 continued from preceding page. continued on next page. 16 17 ei+ eiC control amplifier inputs the pwmin pin must be held at the low level for control using this pin to function. vreg 16 17 300 300 10 11 12 13 14 15 in1C in1+ in2C in2+ in3C in3+ hall sensor inputs a high-level state is recognized when in+ > inC, and a low-level state is recognized under the reverse condition. if noise on the hall sensor signals becomes a problem, insert capacitors between the in+ and inC inputs. v cc 10 12 14 11 13 15 300 300
page. 8 lb11696v pin no. pin name pin description equivalent circuit 23 pwm in pwm pulse input a low-level input specifies the output drive state, and a high-level or open input specifies the output off state. when this pin is used for control, the toc pin voltage must be set to a control amplifier input that results in a 100% duty. vreg 50 k 3.5 k 23 24 f/r forward/reverse input vreg 50 k 3.5 k 24 25 hp hall signal output (this is an open-collector output) one of four output types is selected by the n1 and n2 pin settings. vreg 25 continued from preceding page. continued on next page. 22 s/s start/stop input a low-level input sets the ic to start mode, and a high- level input sets it to stop mode. vreg 3.5 k 22 21 csd constraint protection circuit operating time setting insert a capacitor between this pin and ground. this pin must be connected to ground if the constraint protection circuit is not used. vreg 300 21
page. 9 lb11696v pin no. pin name pin description equivalent circuit 27 n2 hall signal output (hp signal) type selector vreg 50 k 300 27 28 lvs undervoltage protection voltage detection if a 5 v or higher supply voltage is to be detected, set the detection voltage by inserting an appropriate zener diode in series. v cc 28 29 vreg stabilized power supply output (5 v output) insert a capacitor (about 0.1 f) between this pin and ground for stabilization. 29 v cc 30 v cc power supply. insert a capacitor between this pin and ground for stabilization. continued from preceding page. 26 n1 hall signal output (hp signal) type selector vreg 50 k 300 26
page. 10 lb11696v hall sensor signal input/output timing chart areas shown in gray ( ) indicate pwm output. f/r = l in1 in2 in3 uh vh wh ul vl wl f/r = h in1 in2 in3 uh vh wh ul vl wl
page. 11 lb11696v application circuit examples bipolar transistor drive (high side pwm) using a 5 v power supply rf v cc wl uh ul vh vl wh vreg lvs 5 v vm C + ctl toc ei C ei + rfgnd hall logic hall hys amp csd osc f/r s/s lvsd curr lim in2 + in2 C in3 + in3 C v cc f/r hp in1 + in1 C pri driver gnd n1 csd pwmin vreg vreg n1 vref s/s n2 n2 hp logic pwm osc comp pwm pwm in control logic rd rd vreg vreg
page. 12 lb11696v mos transistor drive (low side pwm) using a 12 v power supply rf v cc wh ul uh vl vh wl 12 v vm vreg lvs hall logic hall hys amp csd osc f/r s/s lvsd curr lim in2 + in2 C in3 + in3 C v cc in1 + in1 C pri driver gnd n1 csd vreg vref n2 hp logic comp control logic rd rd rfgnd vreg f/r n1 s/s n2 vreg C + ctl toc ei C ei + pwmin pwm osc pwm pwm in hp vreg
page. 13 lb11696v nmos transistor + pnp transistor drive (low side pwm) using a 12 v power supply with thermal protection implemented using a thermistor v cc wh ul uh vl vh wl vm vreg lvs hall logic hall hys amp csd osc f/r s/s lvsd curr lim in2 + in2 C in3 + in3 C v cc in1 + in1 C pri driver gnd n1 csd vreg vref n2 hp logic comp control logic rd rd f/r n1 s/s n2 vreg vreg 12 v rf rfgnd thermistor C + toc ei C ei + hp pwmin pwm osc pwm pwm in vreg variable duty pulse input
page. 14 lb11696v lb11696v functional description 1. output drive circuit the lb11696v adopts direct pwm drive to minimize power loss in the outputs. the output transistors are always saturated when on, and the motor drive power is adjusted by changing the on duty of the output. the output pwm switching is performed on the uh, vh, and wh outputs. since the ul to wl and uh to wh outputs have the same output form, applications can select either low side pwm or high side pwm drive by changing the way the external output transistors are connected. since the reverse recovery time of the diodes connected to the non-pwm side of the outputs is a problem, these devices must be selected with care. (this is because through currents will flow at the instant the pwm side transistors turn on if diodes with a short reverse recovery time are not used.) 2. current limiter circuit the current limiter circuit limits the output current peak value to a level determined by the equation i = vfr/rf (vrf = 0.25 v typical, rf: current detection resistor). this circuit suppresses the output current by reducing the output on duty. high-precision detection can be implemented by connecting the lines from the rf and rfgnd pins close to the two terminal of the current detection resistor rf. the current limiter circuit includes an internal filter circuit to prevent incorrect current limiter circuit operation due to detecting the output diode reverse recovery current due to pwm operation. although there should be no problems with the internal filter circuit in normal applications, applications should add an external filter circuit (such as an rc low-pass filter) if incorrect operation occurs (if the diode reverse recovery current flows for longer than 1 s). 3. power saving circuit this ic goes to a low-power mode (power saving state) when set to the stop state with the s/s pin. in the power saving state, the bias currents in most of the circuits are cut off. however, the 5 v regulator output (vreg) is still provided in the power saving state. if it is also necessary to cut the hall device bias current, this function can be provided by an application that, for example, connects the hall devices to 5 v through pnp transistors. 4. notes on the pwm frequency the pwm frequency is determined by the capacitor c (f) connected to the pwm pin. f pwm ? 1/(22500 c) if a 2000 pf capacitor is used, the circuit will oscillate at about 22 khz. if the pwm frequency is too low, switching noise will be audible from the motor, and if it is too high, the output power loss will increase. thus a frequency in the range 15 to 50 khz must be used. the capacitor's ground terminal must be placed as close as possible to the ics ground pin to minimize the influence of output noise and other noise sources. 5. control methods the output duty can be controlled by either of the following methods ? control based on comparing the toc pin voltage to the pwm oscillator waveform the low side output transistor duty is determined according to the result of comparing the toc pin voltage to the pwm oscillator waveform. when the toc pin voltage is 1.35 v or lower, the duty will be 0%, and when it is 3.0 v or higher, the duty will be 100%. since the toc pin is the output of the control amplifier (ctl), a control voltage cannot be directly input to the toc pin. normally, the control amplifier is used as a full feedback amplifier (with the ei- pin connected to the toc pin) and a dc voltage is input to the ei+ pin (the ei+ pin voltage will become equal to the toc pin voltage). when the ei+ pin voltage becomes higher, the output duty increases. since the motor will be driven when the ei+ pin is in the open state, a pull-down resistor must be connected to the ei+ pin if the motor should not operate when ei+ is open. when toc pin voltage control is used, a low-level input must be applied to the pwmin pin or that pin connected to ground. to the rf pin current detection resistor to the vreg pin to the s/s pin hall device
page. 15 lb11696v ? pulse control using the pwmin pin a pulse signal can be input to the pwmin pin, and the output can be controlled based on the duty of that signal. note that the output is on when a low level is input to the pwmin pin, and off when a high level is input. when the pwmin pin is open it goes to the high level and the output is turned off. if inverted input logic is required, this can be implemented with an external transistor (npn). when controlling motor operation from the pwmin pin, the eiC pin must be connected to ground, and the ei+ pin must be connected to the toc pin. note that since the pwm oscillator is also used as the clock for internal circuits, a capacitor (about 2000 pf) must be connected to the pwm pin even if the pwmin pin is used for motor control. 6. hall input signals a signal input with an amplitude in excess of the hysteresis (80 mv maximum) is required for the hall inputs. considering the possibility of noise and phase displacement, an even larger amplitude is desirable. if disruptions to the output waveforms (during phase switching) or to the hp output (hall signal output) occur due to noise, this must be prevented by inserting capacitors across the inputs. the constraint protection circuit uses the hall inputs to discriminate the motor constraint state. although the circuit is designed to tolerate a certain amount of noise, care is required when using the constraint protection circuit. if all three phases of the hall input signal system go to the same input state, the outputs are all set to the off state (the ul, vl, wl, uh, vh, and wh outputs all go to the low level). if the outputs from a hall ic are used, fixing one side of the inputs (either the + or C side) at a voltage within the common-mode input voltage range allows the other input side to be used as an input over the 0 v to v cc range. 7. undervoltage protection circuit the undervoltage protection circuit turns one side of the outputs (uh, vh, and wh) off when the lvs pin voltage falls below the minimum operation voltage (see the electrical characteristics). to prevent this circuit from repeatedly turning the outputs on and off in the vicinity of the protection operating voltage, this circuit is designed with hysteresis. thus the output will not recover until the operating voltage rises 0.45 v (typical). the protection operating voltage detection level is set up for 5 v systems. the detected voltage level can be increased by shifting the voltage by inserting a zener diode in series with the lvs pin to shift the detection level. the lvs influx current during detection is about 75 a. to increase the diode current to stabilize the zener diode voltage rise, insert a resistor between the lvs pin and ground. if the lvs pin is left open, the internal pull-down resistor will result in the ic seeing a ground level input, and the output will be turned off. therefore, a voltage in excess of the lvs circuit clear voltage (about 4.35 v) must be applied to the lvs pin if the application does not use the undervoltage protection circuit. the maximum rating for the lvs pin applied voltage is 18 v. 8. constraint protection circuit when the motor is physically constrained (held stopped), the csd pin external capacitor is charged (to about 3.0 v) by a constant current of about 2.5 a and is then discharged (to about 1.0 v) by a constant current of about 0.14 a. this process is repeated, generating a sawtooth waveform. the constraint protection circuit turns motor drive on and off repeatedly based on this sawtooth waveform. (the uh, vh, and wh side outputs are turned on and off.) motor drive is on during the period the csd pin external capacitor is being charged from about 1.0 v to about 3.0 v, and motor drive is off during the period the csd pin external capacitor is being discharged from about 3.0 v to about 1.0 v. the ic and the motor are protected by this repeated drive on/off operation when the motor is physically constrained. the motor drive on and off times are determined by the value of the connected capacitor c (in f). tcsd1 (drive on period) ? 0.8 c (seconds) tcsd2 (drive off period) ? 14.3 c (seconds) when a 0.47 f capacitor is connected externally to the csd pin, this iterated operation will have a drive on period of about 0.38 seconds and a drive off period of about 6.7 seconds. to the power supply detected to the lvs pin
page. 16 lb11696v while the motor is turning, the discharge pulse signal (generated once for each hall input period) that is created by combining the hall inputs internally in the ic discharges the csd pin external capacitor. since the csd pin voltage does not rise, the constraint protection circuit does not operate. when the motor is physically constrained, the hall inputs do not change and the discharge pulses are not generated. as a result, the csd pin external capacitor is charged by a constant current of 2.5 a to about 3.0 v, at which point the constraint protection circuit operates. when the constraint on the motor is released, the constraint protection function is released. connect the csd pin to ground if the constraint protection circuit is not used. 9. forward/reverse direction switching this ic is designed so that through currents (due to the output transistor off delay time when switching) do not flow in the output when switching directions when the motor is turning. however, if the direction is switched when the motor is turning, current levels in excess of the current limiter value may flow in the output transistors due to the motor coil resistance and the motor back emf state when switching. therefore, designers must consider selecting external output transistors that are not destroyed by those current levels or only switching directions after the speed has fallen below a certain speed. 10. handling different power supply types when this ic is operated from an externally supplied 5 v power supply (4.5 to 5.5 v), short the v cc pin to the vreg pin and connect them to the external power supply. when this ic is operated from an externally supplied 12 v power supply (8 to 17 v), connect the v cc pin to the power supply. (the vreg pin will generate a 5 v level to function as the control circuit power supply.) 11. power supply stabilization since this ic uses a switching drive technique, the power supply line level can be disturbed easily. therefore capacitors with adequate capacitance to stabilize the power supply line must be inserted between v cc and ground. if diodes are inserted in the power supply lines to prevent destruction if the power supply is connected with reverse polarity, the power supply lines are even more easily disrupted, and even larger capacitors are required. if the power supply is turned on and off by a switch, and if there is a significant distance between that switch and the stabilization capacitor, the supply voltage can be disrupted significantly by the line inductance and surge current into the capacitor. as a result, the withstand voltage of the device may be exceeded. in application such as this, the surge current must be suppressed and the voltage rise prevented by not using ceramic capacitors with a low series impedance, and by using electrolytic capacitors instead. 12. vreg stabilization to stabilize the vreg voltage, which is the control circuit power supply, a 0.1 f or larger capacitor must be inserted between the vreg pin and ground. the ground side of this capacitor must connected to the ic ground pin with a line that is as short as possible.
lb11696v www.onsemi.com 17 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. ordering information device package shipping (qty / packing) lb11696v-mpb-e ssop30 (275mil) (pb-free) 48 / fan-fold lb11696v-tlm-e ssop30 (275mil) (pb-free) 1000 / tape & reel LB11696V-TRM-E ssop30 (275mil) (pb-free) 1000 / tape & reel ? for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. h ttp://www.onsemi.com/pub_lin k/collateral/brd8011-d.pdf

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